An automatic data processing system typically contains a multiplicity of various relatively elementary types of logic circuit arrangements, or "logic gates", interconnected for computing relatively complex data processing functions as are desired by the users. Each of the logic gates typically can compute only a prescribed one of a group of many possible types of relatively elementary binary logic functions of binary input variables. A "binary input variable" is a logic variable which can have the logic value of 1 or 0, corresponding to TRUE or FALSE, respectively. In an electrical logic circuit, each such input variable is represented by a voltage signal at a voltage level that can be either relatively HIGH or LOW, respectively, to represent the respective logic 1 or logic 0 value of the corresponding input variable. Each such input voltage signal is applied to an input terminal of the logic gate, whereby an output terminal of the gate delivers a binary output signal voltage at a HIGH or LOW level, representing a logic 1 or logic 0, respectively, corresponding to the prescribed logic function of the gate, that is, as a function of the input variables.
Semiconductor integrated circuits are typically used for implementing the various logic gates in a data processing system. Each of the gates is implemented by a group of transistors, together with electrical interconnections between them, integrated in a semiconductor body at a major surface thereof. The various gates themselves are also electrically interconnected to form a logic circuit for computing the more complex data processing functions than those which are computed by a single logic gate, as are desired by the consuming public.
In such logic circuits, it is often desired to have a circuit arrangement of transistors for computing the EXCLUSIVE OR logic function of two binary input variables, say A and B, and it is also often desired to have a circuit arrangment for computing the EXCLUSIVE NOR function. Such arrangements are known as "EXCLUSIVE OR gates" and "EXCLUSIVE NOR gates", respectively. By the EXCLUSIVE OR function, it is meant that the output of the logic gate should be at a HIGH level--i.e., binary 1--if and only if either A or B is binary 1 but not both; otherwise, the output should be LOW. Thus the EXCLUSIVE OR is binary 1 if and only if A is not equal to B, and binary 0 if and only if A and B are equal (A=B). By the EXCLUSIVE NOR function is meant that the output of the logic gate should be HIGH (binary 1) if and only if A and B are equal (both HIGH, or both LOW), and is LOW (binary 0) if and only if the inputs A and B are unequal (one of them HIGH, the other of them LOW); whereas the EXCLUSIVE OR function of A and B is thus binary 1 if and only if A and B are unequal, and is binary 0 if and only if A and B are equal.
The logical inverse or complement of any binary logic variable X is defined as (1-X) and is denoted by X. Thus, in terms of corresponding electrical signals, when X is HIGH, X is LOW; and when X is LOW, X is HIGH. Accordingly, the EXCLUSIVE OR function is the complement or inverse of the EXCLUSIVE NOR function, and the EXCLUSIVE OR function of input variables A and B can be represented mathematically as being equal to (AB+AB). Moreover, whenever A and B are equal, A and B are unequal, as are A and B. Thus the EXCLUSIVE OR function of inputs A and B is the same as the EXCLUSIVE NOR function of inputs A and B as well as of inputs A and B. Accordingly, a logic gate which operates an EXCLUSIVE OR gate for inputs A and B can operate as an EXCLUSIVE NOR gate for inputs A and B, as well as for inputs A and B. Thus, by changing one and only one of the inputs of an EXCLUSIVE OR gate into the complement of that input, the gate operates as an EXCLUSIVE NOR gate, and similarly an EXCLUSIVE NOR gate operates as an EXCLUSIVE OR gate by changing one and only one of the inputs into its complement.
Logic gates of all types, including the EXCLUSIVE OR gate, generally fall into two categories, static and dynamic. In a static logic gate, the outputs are valid (have the desired logic values) whenever all the input variables are valid. In a dynamic logic gate, however, because of the need for precharging, the outputs are not always valid even when all the input variables are valid; and these gates will not be considered further herein.
Static logic gates can be built in complementary field effect transistor (FET) technology, that is, each logic gate contains both n-type conductivity (or n-channel) FETs and p-type conductivity (or p-channel) FETs in order to implement the prescribed logic function of the gate. Complementary FET technology is also known as "CMOS", an acrostic for complementary metal oxide semiconductor, since such technology utilizes both p-channel MOS transistors (PMOS) and n-channel MOS transistors (NMOS). Each such MOS transistor operates as a switching element, having a gate electrode terminal as its control terminal, and having a source terminal and a drain terminal as its controlled terminals. That is, input signals are applied to the transistor's gate electrode terminal in order to control the resistance of, and hence the flow of current between, its source and drain terminals. More particularly, in a static CMOS logic gate, there is a PMOS portion which contains a network of PMOS transistors for driving the voltage of the output terminal of the logic gate to a HIGH or LOW level depending upon the specific combination of various inputs delivered to the input (gate) terminals of the PMOS transistors, and there is an NMOS portion which contains a network of NMOS transistors likewise for driving the voltage of the output terminal to the HIGH or LOW level. Accordingly, each network of NMOS and of PMOS transistors is called a logic network, and each of the NMOS and PMOS transistors is called a driver transistor. In addition, either the NMOS portion or the PMOS portion (but ordinarily not both simultaneously) may have no tendency to drive the voltage at the output terminal to any particular level, whereby the output is driven solely by only one of the PMOS and NMOS portions, depending upon the specific logic levels of the various inputs and the particular designs of the PMOS and NMOS networks. A static CMOS logic gate has the advantage that, except for the relatively very short time intervals during which the input variables are making transitions from one logic value to another, no current flows through the gate, and hence no power is consumed by the gate.
It is known in the prior art (FIG. 1) that an EXCLUSIVE OR logic gate 10 can be implemented in static CMOS technology by means of a PMOS portion, having a logic network consisting of a pair of cross-coupled PMOS transistors, T1 and T2, together with an NMOS portion, having a logic network consisting of a pair of cross-coupled NMOS transistors T3 and T4, as illustrated by the logic gate circuit arrangement 10 in FIG. 1. By "cross-coupled", it is meant that a gate terminal of each transistor is connected to the source or drain terminal of the other transistor. Here NMOS transistors are denoted by "n"; PMOS transistors by "p". The output of the circuit arrangement 10, implementing this EXCLUSIVE OR logic gate, is developed at output terminal X in response to input signals A and B. This output can be mathematically represented as X=AB+AB.
The circuit 10 suffers from an undesirable characteristic which occurs when both inputs A and B are initially LOW and A then goes from LOW to HIGH, and hence when the voltage at the output terminal X is supposed to go from LOW to HIGH. The undesirable characteristic may be seen from the following considerations. When both A and B are initially LOW, NMOS transistor T3 is OFF, but NMOS transistor T4 is ON because its gate electrode is controlled by the HIGH level of the A signal, which is the complement of the input A, as inverted by the inverter I. Both PMOS transistors T1 and T2 are OFF due to the back gate bias effect. Thus the output terminal X is initially LOW, as it should be for an EXCLUSIVE OR gate, for several consistent reasons: (1) the LOW level of input A blocks any current through the transistor T1 to X, (2) the LOW level of input B blocks any current through the transistor T2 to X, (3) the HIGH level of A cannot pass through the (initially OFF) transistor T3, and (4) the LOW level of B passes through the (initially ON) transistor T4. Then as the input A attempts to go HIGH at input terminal 11, it reduces the back gate bias effect on T1 and causes T1 to turn ON. The path through transistors T4 and T1, which are now both ON, undesirably enables the still LOW input B to conflict at terminal 11 with the input A and prevents its complement A from going LOW and thus from turning OFF transistor T4. Accordingly, unless the input signal A is reliably stronger than B (as weakened by having been delivered through T4 and T1 in the ON condition), the transistor T4 remains ON and the output terminal X tends to remain at the (weakened) LOW level of input B. Accordingly, X does not reliably go HIGH as it should for an EXCLUSIVE OR gate in response to a HIGH A and a LOW B. Although it is probable that the HIGH level of input A would ordinarily overpower the LOW level of input B and hence A would ordinarily turn T4 OFF as desired, nevertheless the conflict is still present and is undesirable because it tends to reduce the safety margin of reliability. Similar problems are encountered with static CMOS EXCLUSIVE NOR gates. Thus it would be desirable to have an EXCLUSIVE OR and EXCLUSIVE NOR gate in static CMOS which does not suffer from this problem, but without unduly increasing the number of required transistors and hence without unduly increasing the required precious area of underlying semiconductor in which the transistors are integrated.